8051 XRL Instruction

Logical Exclusive-OR

Instruction	XRL dest-byte,src-byte
Function	Logical Exclusive-OR for byte variables
Description	XRL performs the bitwise logical Exclusive-OR operation between the indicated variables, storing the results in the destination. No flags are affected. The two operands allow six addressing mode combinations. When the destination is the Accumulator, the source can use register, direct, register-indirect, or immediate addressing; when the destination is a direct address, the source can be the Accumulator or immediate data. Note: When this instruction is used to modify an output port, the value used as the original port data is read from the output data latch, not the input pins.
Example	If the Accumulator holds 0C3H (1100001lB) and register 0 holds 0AAH (10101010B) then the instruction, XRL A,R0 leaves the Accumulator holding the value 69H (01101001B). When the destination is a directly addressed byte, this instruction can complement combinations of bits in any RAM location or hardware register. The pattern of bits to be complemented is then determined by a mask byte, either a constant contained in the instruction or a variable computed in the Accumulator at run-time. The following instruction, XRL P1,#00110001B complements bits 5, 4, and 0 of output Port 1.
Variants	XRL A,Rn XRL A,direct address XRL A,@Ri XRL A,#immediate data XRL direct address,A XRL direct address, #immediate data

Instruction	XRL A,Rn
Bytes	1
Cycles	1
Encoding	0 1 1 0 1 n n n
Operation	A = A XOR Rn
Flags Affected	C AC F0 RS1 RS0 OV P
Example	XRL A, R4
Bytes: Number of bytes required to encode the instruction. Cycles: Number of instruction cycles required to execute the instruction. Note that there are 12 oscillator cycles to one instruction cycle on a standard 8051. Encoding: Lists the byte encoding for the instruction. Operation: Lists, step-by-step, the operations performed by the instruction. Flags Affected: are highlighted in Bold

Instruction	XRL A,direct address
Bytes	2
Cycles	1
Encoding	0 1 1 0 0 1 0 1 A7...A0
Operation	A = A XOR (direct address)
Flags Affected	C AC F0 RS1 RS0 OV P
Example	XRL A, 40h
Bytes: Number of bytes required to encode the instruction. Cycles: Number of instruction cycles required to execute the instruction. Note that there are 12 oscillator cycles to one instruction cycle on a standard 8051. Encoding: Lists the byte encoding for the instruction. Operation: Lists, step-by-step, the operations performed by the instruction. Flags Affected: are highlighted in Bold

Instruction	XRL A,@Ri
Bytes	1
Cycles	1
Encoding	0 1 1 0 0 1 1 i
Operation	A = A XOR (Ri)
Flags Affected	C AC F0 RS1 RS0 OV P
Example	XRL A, @R0
Bytes: Number of bytes required to encode the instruction. Cycles: Number of instruction cycles required to execute the instruction. Note that there are 12 oscillator cycles to one instruction cycle on a standard 8051. Encoding: Lists the byte encoding for the instruction. Operation: Lists, step-by-step, the operations performed by the instruction. Flags Affected: are highlighted in Bold

Instruction	XRL A,#immediate data
Bytes	2
Cycles	1
Encoding	0 1 1 0 0 1 0 0 D7...D0
Operation	A = A XOR immediate data
Flags Affected	C AC F0 RS1 RS0 OV P
Example	XRL A, #3Fh
Bytes: Number of bytes required to encode the instruction. Cycles: Number of instruction cycles required to execute the instruction. Note that there are 12 oscillator cycles to one instruction cycle on a standard 8051. Encoding: Lists the byte encoding for the instruction. Operation: Lists, step-by-step, the operations performed by the instruction. Flags Affected: are highlighted in Bold

Instruction	XRL direct address,A
Bytes	2
Cycles	1
Encoding	0 1 1 0 0 0 1 0 A7...A0
Operation	(direct address) = (direct address) XOR A
Flags Affected	C AC F0 RS1 RS0 OV P
Example	XRL 40h, A
Bytes: Number of bytes required to encode the instruction. Cycles: Number of instruction cycles required to execute the instruction. Note that there are 12 oscillator cycles to one instruction cycle on a standard 8051. Encoding: Lists the byte encoding for the instruction. Operation: Lists, step-by-step, the operations performed by the instruction. Flags Affected: are highlighted in Bold

Instruction	XRL direct address, #immediate data
Bytes	3
Cycles	2
Encoding	0 1 1 0 0 0 1 1 A7...A0 D7...D0
Operation	(direct address) = (direct address) XOR immediate data
Flags Affected	C AC F0 RS1 RS0 OV P
Example	XRL 30h, #77h
Bytes: Number of bytes required to encode the instruction. Cycles: Number of instruction cycles required to execute the instruction. Note that there are 12 oscillator cycles to one instruction cycle on a standard 8051. Encoding: Lists the byte encoding for the instruction. Operation: Lists, step-by-step, the operations performed by the instruction. Flags Affected: are highlighted in Bold

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Related topics:
8051 Logical Operation Instructions   |   8051 ANL Instruction   |   8051 ORL Instruction   |   8051 CLR Instruction   |   8051 CPL Instruction   |   8051 RL Instruction   |   8051 RR Instruction   |   8051 RLC Instruction   |   8051 RRC Instruction   |   8051 SWAP Instruction

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List of topics: 8051

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