Return from Interrupt
| Instruction | RETI |
|---|---|
| Function | Return from Interrupt |
| Bytes | 1 |
| Cycles | 2 |
| Encoding | 0 0 1 1 0 0 1 0 |
| Operation | PC15-8 = (SP) SP = SP - 1 PC7-0 = (SP) SP = SP - 1 |
| Description | RETI pops the high- and low-order bytes of the PC successively from the stack and restores the interrupt logic to accept additional interrupts at the same priority level as the one just processed. The Stack Pointer is left decremented by two. No other registers are affected; the PSW is not automatically restored to its pre-interrupt status. Program execution continues at the resulting address, which is generally the instruction immediately after the point at which the interrupt request was detected. If a lower- or same-level interrupt was pending when the RETI instruction is executed, that one instruction is executed before the pending interrupt is processed. |
| Flags Affected | C AC F0 RS1 RS0 OV P |
| Example | The Stack Pointer originally contains the value 0BH. An interrupt was detected during the instruction ending at location 0122H. Internal RAM locations 0AH and 0BH contain the values 23H and 01H, respectively. The following instruction, RETI leaves the Stack Pointer equal to 09H and returns program execution to location 0123H. |
| Bytes: Number of bytes required to encode the instruction. Cycles: Number of instruction cycles required to execute the instruction. Note that there are 12 oscillator cycles to one instruction cycle on a standard 8051. Encoding: Lists the byte encoding for the instruction. Operation: Lists, step-by-step, the operations performed by the instruction. Flags Affected: are highlighted in Bold | |
Related topics:
8051 Program Branching Instructions | 8051 ACALL Instruction | 8051 LCALL Instruction | 8051 RET Instruction | 8051 JMP Instruction | 8051 AJMP Instruction | 8051 LJMP Instruction | 8051 SJMP Instruction | 8051 JZ Instruction | 8051 JNZ Instruction | 8051 CJNE Instruction | 8051 DJNZ Instruction | 8051 NOP Instruction
List of topics: 8051
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