Wednesday, March 2, 2016

8051 NOP Instruction

No Operation

FunctionNo Operation
Encoding0 0 0 0 0 0 0 0
OperationPC = PC + 1
DescriptionExecution continues at the following instruction. Other than the PC, no registers or flags are affected.
Flags AffectedC AC F0 RS1 RS0 OV P
ExampleA low-going output pulse on bit 7 of Port 2 must last exactly 5 cycles. A simple SETB/CLR sequence generates a one-cycle pulse, so four additional cycles must be inserted. This may be done (assuming no interrupts are enabled) with the following instruction sequence,
CLR P2.7
Bytes: Number of bytes required to encode the instruction.
Cycles: Number of instruction cycles required to execute the instruction. Note that there are 12 oscillator cycles to one instruction cycle on a standard 8051.
Encoding: Lists the byte encoding for the instruction.
Operation: Lists, step-by-step, the operations performed by the instruction.
Flags Affected: are highlighted in Bold

Related topics:
8051 Program Branching Instructions   |   8051 ACALL Instruction   |   8051 LCALL Instruction   |   8051 RET Instruction   |   8051 RETI Instruction   |   8051 JMP Instruction   |   8051 AJMP Instruction   |   8051 LJMP Instruction   |   8051 SJMP Instruction   |   8051 JZ Instruction   |   8051 JNZ Instruction   |   8051 CJNE Instruction   |   8051 DJNZ Instruction

List of topics: 8051

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