Sunday, February 28, 2016

8051 Instruction Cycle

Fetch, Decode and Execute

An instruction cycle (sometimes called fetch-decode-execute cycle) is the basic operation cycle of a computer. It is the process by which a computer retrieves a program instruction from its memory, determines what actions the instruction requires, and carries out those actions. This cycle is repeated continuously by the central processing unit (CPU), from bootup to when the computer is shut down.

In 8051, the instruction cycle is executed sequentially: each instruction is completely processed before the next one is started.

The cycle starts immediately when power is applied to the system using an initial PC value (0000H) that is predefined for 8051.
A cycle includes:
1. Instruction Fetch (IF)
2. Instruction Decode (ID)
3. Data Fetch (DF) / Operand Fetch (OF)
4. Instruction Execution (EX)
5. Result Return (RR) / Store (ST)

Fetch the Instruction:
- The CPU sends Program Counter (PC) to the Memory Address Register (MAR)
- CPU activates tri-state buffer so MAR contents are placed on the address bus.
- CPU sends READ command on the control bus, R/W = 1 and CE = 1 to memory, to indicate it wants to do a read.
- In response to the read command (with address equal to PC), the memory returns the data stored at the memory location indicated by PC on the databus.
- Memory sends ACK = 1.
- The CPU copies the data from the databus into its Memory Data Register (MDR) (also known as Memory Buffer Register (MBR))
- A fraction of a second later, the CPU copies the data from the MDR to the Instruction Register (IR)
- CPU sets CE = 0 to memory indicate it's done with fetching the instruction
- The PC is incremented so that it points to the following instruction in memory. This step prepares the CPU for the next cycle.

Decode the Instruction:
The decoding process allows the CPU to determine what instruction is to be performed, so that the CPU can tell how many operands it needs to fetch in order to perform the instruction. The opcode fetched from the memory is decoded for the next steps and moved to the appropriate registers. The bits used for the opcode are used to determine how the instruction should be executed.

Fetching the Operand:
Fetch operands from memory if necessary: If any operands are memory addresses, initiate memory read cycles to read them into CPU registers. If an operand is in memory, not a register, then the memory address of the operand is known as the effective address (EA) for short. The fetching of an operand can therefore be denoted as Register ← Memory [EA].

Executing the Instruction:
Perform the function of the instruction. If arithmetic or logic instruction, utilize the ALU circuits to carry out the operation on data in registers. This is the only stage of the instruction cycle that is useful from the perspective of the end user. Everything else is overhead required to make the execute stage happen.

Storing the Result:
Store result in memory if necessary: If destination is a memory address, initiate a memory write cycle to transfer the result from the CPU to memory. Depending on the situation, the CPU may or may not have to wait until this operation completes. If the next instruction does not need to access the memory chip where the result is stored, it can proceed with the next instruction while the memory unit is carrying out the write operation.

Related topics:
8051 Instruction Set Overview   |   8051 Machine Cycle   |   8051 Instruction Set Summary   |   8051 Arithmetic Operation Instructions   |   8051 Logical Operation Instructions   |   8051 Data Transfer Instructions   |   8051 Boolean Variable Manipulation Instructions   |   8051 Program Branching Instructions   |   8051 Instruction Opcode   |   8051 Instructions that Affect Flag Settings   |   8051 Instructions and Examples

List of topics: 8051

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