Thursday, March 31, 2016

ROM and RAM Memory

Semiconductor Memory

Semiconductor memories are used as primary storage for code and data. Semiconductor memories are connected directly to the CPU and they are the memory that the CPU first asks for information (code and data). For this reason, semiconductor memories are sometimes referred to as primary memory. The most widely used semiconductor memories are ROM and RAM.

The number of bits that a semiconductor memory chip can store is called chip capacity. The number of bits that each location within the memory chip can hold is always equal to the number of data pins on the chip. The number of locations within a memory IC always equals 2 to the power of the number of address pins. Therefore, the total number of bits that a memory chip can store is equal to the number of locations times the number of data bits per location. The speed at which its data can be accessed of the memory chip is commonly referred to as its access time. The access time of memory chips varies from a few nanoseconds to hundreds of nanoseconds, depending on the IC technology used in the design and fabrication process.

ROM: ROM is a type of memory that does not lose its contents when the power is turned off. For this reason, ROM is also called nonvolatile memory.

PROM and OTP: PROM refers to the kind of ROM that the user can burn information into. In other words, PROM is a user-programmable memory. For every bit of the PROM, there exists a fuse. PROM is programmed by blowing the fuses. If the information burned into PROM is wrong, that PROM must be discarded since its internal fuses are blown permanently. For this reason, PROM is also referred to as OTP (one-time programmable). Programming ROM, also called burning ROM, requires special equipment called a ROM burner or ROM programmer.

EPROM and UV-EPROM: EPROM was invented to allow making changes in the contents of PROM after it is burned. In EPROM, one can program the memory chip and erase it thousands of times. A widely used EPROM is called UV-EPROM, where UV stands for ultraviolet. The only problem with UV-EPROM is that erasing its contents can take up to 20 minutes.

EEPROM: EEPROM has several advantages over EPROM, such as the fact that its method of erasure is electrical and therefore instant, as opposed to the 20-minute erasure time required for UV-EPROM. In addition, in EEPROM one can select which byte to be erased, in contrast to UV-EPROM, in which the entire contents of ROM are erased. However, the main advantage of EEPROM is that one can program and erase its contents while it is still in the system board. It does not require physical removal of the memory chip from its socket. In other words, unlike UV-EPROM, EEPROM does not require an external erasure and programming device.

Flash Memory: flash EPROM has become a popular user-programmable memory chip, and for good reasons. First, the erasure of the entire contents takes less than a second, or one might say in a flash, hence its name, flash memory. In addition, the erasure method is electrical, and for this reason it is sometimes referred to as flash EEPROM. To avoid confusion, it is commonly called flash memory. The major difference between EEPROM and flash memory is that when flash memory’s contents are erased, the entire device is erased, in contrast to EEPROM, where one can erase a desired section or byte. Although in some flash memories recently made available the contents are divided into blocks and the erasure can be done block by block, unlike EEPROM, flash memory has no byte erasure option.

Mask ROM: Mask ROM refers to a kind of ROM in which the contents are programmed by the IC manufacturer. In other words, it is not a user-programmable ROM. The term mask is used in IC fabrication. The main advantage of mask ROM is its cost, since it is significantly cheaper than other kinds of ROM.

RAM: RAM memory is called volatile memory since cutting off the power to the IC results in the loss of data. Sometimes RAM is also referred to as RAWM (read and write memory), in contrast to ROM, which cannot be written to.

SRAM: Storage cells in static RAM memory are made of flip-flops and therefore do not require refreshing in order to keep their data. The problem with the use of flip-flops for storage cells is that each cell requires at least 6 transistors to build, and the cell holds only 1 bit of data. In recent years, the cells have been made of 4 transistors, which still is too many.

NVRAM: Whereas SRAM is volatile, there is a new type of nonvolatile RAM called NV-RAM. Like other RAMs, it allows the CPU to read and write to it, but when the power is turned off the contents are not lost. NV-RAM combines the best of RAM and ROM: the read and write ability of RAM, plus the non-volatility of ROM. It uses an internal lithium battery as a backup energy source. The internal lithium power source is used to retain the NV-RAM contents only when the external power source is off.

Checksum Byte ROM: To ensure the integrity of the ROM contents, every system must perform the checksum calculation. The process of checksum will detect any corruption of the contents of ROM. One of the causes of ROM corruption is current surge, either when the system is turned on or during operation. To ensure data integrity in ROM, the checksum process uses what is called a checksum byte. The checksum byte is an extra byte that is tagged to the end of a series of bytes of data. To calculate the checksum byte of a series of bytes of data, the following steps can be taken.
  • Add the bytes together and drop the carries
  • Take the 2′s complement of the total sum, and that is the checksum byte, which becomes the last byte of the series
  • To perform the checksum operation, add all the bytes, including the checksum byte. The result must be zero. If it is not zero, one or more bytes of data have been changed (corrupted).
Dynamic RAM: Intel Corporation introduced the first dynamic RAM (random access memory) and it used a capacitor to store each bit. Using a capacitor to store data cuts down the number of transistors needed to build the cell; however, it requires constant refreshing due to leakage. This is in contrast to SRAM (static RAM), whose individual cells are made of flip-flops. The use of capacitors as storage cells in DRAM results in much smaller net memory cell size.
The major advantages are high density (capacity), cheaper cost per bit, and lower power consumption per bit. The disadvantage is that it must be refreshed periodically because the capacitor cell loses its charge; furthermore, while DRAM is being refreshed, the data cannot be accessed. This is in contrast to SRAM’s whose contents can be accessed at any time.

DRAM has a problem of packing a large number of cells into a single chip with the normal number of pins assigned to addresses. A 64K-bit chip (64Kxl) must have 16 address pins and 1 data pin, power, ground and control pins. To reduce the number of pins needed for addresses, multiplexing/demultiplexing is used. The method used is to split the address in half and send in each half of the address through the same pins, thereby requiring fewer address pins. Internally, the DRAM structure is divided into a square of rows and columns. The first half of the address is called the row and the second half is called the column. For example, in the case of DRAM of 64Kxl organization, the first half of the address is sent in through the 8 pins AO – A7, and by activating RAS (row address strobe), the internal latches inside DRAM grab the first half of the address. After that, the second half of the address is sent in through the same pins, and by activating CAS (column address strobe), the internal latches inside DRAM latch the second half of the address. This results in using 8 pins for addresses plus RAS and CAS, for a total of 10 pins, instead of the 16 pins that would be required without multiplexing. To access a bit of data from DRAM, both row and column addresses must be provided. Due to the complexities associated with DRAM interfacing (RAS, CAS, the need for multiplexer and refreshing circuitry), there are DRAM controllers designed to make DRAM interfacing much easier. 16Kx4 DRAM has 7 pins (AO – A6) for the address pins, 2 pins for RAS and CAS and 4 pins for the data bus.

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